In the evaluation of product wafers in a semiconductor production environment, a wafer scanning system is employed which uses a site to site comparison technique to determine if a difference exists between adjacent dice. If a difference exists, the location of that difference is noted and is marked as a defect. To perform this task the system scans a "swath" of a predetermined height across the surface of a wafer, from right to left and left to right, comparing like areas of adjacent dice to make a determination if defects are present. After completion of the current swath it indexes to the next swath area and scans it, and so on, until either the wafer is completed or a defect limit set at the wafer level is reached. Multiple swaths are necessary to scan the entire surface of the wafer. In the course of processing and evaluating wafers, such wafers exist which exhibit very high levels of defects in isolated portions of the wafer, see generally FIG. 3. In order to improve throughput, an arbitrary limit is placed on the system to account for, by example, no more than 5000 defects, since the throughput of the system is inversely proportional to the number of caught defects. If the 5000 limit is obtained the system stops scanning at the current location, (even if it is the first swath), rejects the wafer and begins scanning the next wafer in the queue. The difficulty with this system is information about the remainder of the wafer is lost, or at least never acquired, and vital areas of interest are left without data. Since the wafer containing the high quantity of defect is likely to be one which needs to be studied further for source and types of defects, a need is seen to exist for a wafer scanning system and technique which is not based on a defect limit set at the wafer level and which allows completion of the defect analysis of the wafer unit being tested.
Therefore, it is a primary object of the present invention to provide a wafer scanning system and technique which is not based on a defect limit set at the wafer level and which allows completion of the defect analysis of the wafer unit being tested.